Field-programmable gate arrays (FPGAs) have important advantages, but compilation consisting of full-detail synthesis, placement, and routing can require hours or even days, which is slow for some use cases and is a productivity bottleneck for many others. In addition, FPGA compilation is typically only computationally feasible on large machines, whereas compilers for graphics-processing units (GPUs) can run on small microprocessors even at runtime. It is desirable for FPGA systems to also be able to take advantage of the enhanced application portability, security, and target- and runtime-specific optimizations.
Specialized, coarse-grain virtual architectures (also known as overlays) can reduce the effort required for FPGA compilation by bringing the underlying fine-grain architecture of FPGAs up to the level of a given application, providing an abstraction over the FPGA. Because applications may change over time, either due to changing workloads or designer additions, or to handle optimizations introduced using runtime information, overlays should be flexible enough to support such changes to avoid the need to fall back to full-detail FPGA compilation. However, providing for this flexibility results in area overhead to include functional resources that aren't immediately used, or routing resources for connections that aren't immediately required. Therefore, there is a need to identify architectures that provide appropriate overhead and flexibility tradeoffs for the particular application when using overlays for FPGA design.